A. Field of the Invention
This invention relates to memory address circuitry, in general, and to word select circuitry for eliminating double RAM row addressing in particular.
B. Description of the Prior Art
As is known in the art, for static cells, the column lines or bit lines are charged prior to the time that information is read from the cell. Discharging may be accomplished through the use of a field effect device of either the enhancement-type or depletion type during dead time; this time generally being the time when a control signal indicates that the memory has not been selected.
A problem that is encountered in memories, particularly as access time is decreased, is that of multiple selection or double row addressing. Often address buffers are utilized to generate a complement of an address, thus for each address bit its complement is also used in the decoders. However, if the complement bits are delayed from the true address bits (because of delays in the address buffers) multiple selection can occur.